Accretech ChaMP-332 Chemical Mechanical Polishing System

Overview

The Accretech ChaMP-332 is a production-grade chemical mechanical polishing (CMP) system engineered for high-volume semiconductor manufacturing environments requiring sub-micron planarization precision on 300 mm and 200 mm silicon wafers. Built upon Accretech’s proprietary pneumatic floating carrier architecture, the ChaMP-332 implements Couette-flow–based slurry delivery and real-time pressure modulation across discrete annular zones to achieve uniform material removal rates (MRR) and exceptional within-wafer non-uniformity (WIWNU) control. Unlike conventional fixed-head or hydraulic carriers, the ChaMP-332’s air-bearing carrier head utilizes a dynamically stabilized gas film that decouples mechanical compliance from thermal drift and mechanical hysteresis—enabling repeatable nanoscale thickness control across full-wafer maps. The system is designed to support dual-damascene copper barrier polishing, low-k dielectric planarization, and advanced packaging applications such as TSV (through-silicon via) wafer thinning, where edge exclusion ≤1.0 mm and localized pressure tuning are critical process requirements.

Key Features

• Pneumatic floating carrier head with independently controlled ring-shaped pressure zones for deterministic edge profile shaping and center-to-edge MRR compensation
• Dual-stage air-film stabilization: primary load-bearing air cushion + secondary safety bladder ensuring stable low-pressure operation (<10 kPa) during transient events
• Modular carrier head design enabling full ring replacement in under 60 seconds—no carrier disassembly or recalibration required
• Integrated optical endpoint detection system utilizing broadband reflectometry (400–800 nm) with real-time spectral deconvolution for multi-layer stack monitoring
• ChaMP wet-cleaning module with programmable multi-nozzle rinse, megasonic agitation, and N₂ dry-blow sequences compliant with SEMI F47 chemical resistance standards
• Real-time slurry flow monitoring with Coriolis mass flow sensors and temperature-compensated viscosity feedback loops

Sample Compatibility & Compliance

The ChaMP-332 accommodates standard 300 mm and 200 mm silicon wafers with front-side flatness ≤2 µm TTV and backside roughness <0.5 µm Ra. It supports oxide, silicon nitride, tungsten, copper, cobalt, and low-k dielectric films (k < 3.0), including porous organosilicate glass (OSG). Process recipes are validated per ASTM F2613 (Standard Test Method for Measuring Planarization Performance of CMP Slurries) and aligned with JEDEC JESD22-A108 for thermal cycling reliability of polished structures. System hardware meets SEMI S2/S8 safety and ergonomics requirements; software architecture supports 21 CFR Part 11-compliant electronic records, role-based access control, and automated audit trail generation for GMP/GLP environments.

Software & Data Management

The ChaMP-332 runs on a deterministic real-time control platform based on Windows Embedded Industry OS, featuring synchronized I/O timing resolution ≤100 µs. The operator interface provides recipe-driven workflow management with version-controlled parameter sets, cross-tool recipe portability (via SEMI E54.1 XML schema), and integrated metrology data ingestion from compatible surface profilers and ellipsometers. All process logs—including pressure transients, slurry flow profiles, optical endpoint spectra, and motor torque signatures—are timestamped, digitally signed, and stored in encrypted SQLite databases with configurable retention policies. Remote diagnostics and predictive maintenance alerts are enabled via TLS 1.2–secured OPC UA connectivity.

Applications

• Copper interconnect planarization in 7 nm to 28 nm logic and memory nodes
• Low-k dielectric polish for BEOL integration with minimal dishing and erosion
• Wafer-level packaging (WLP) and fan-out RDL (redistribution layer) planarization
• TSV wafer thinning and backside metallization preparation
• Compound semiconductor substrates (GaAs, SiC, GaN) requiring low-stress, particle-free surface finishing
• MEMS device fabrication involving multi-material stack planarization

FAQ

What wafer sizes does the ChaMP-332 support?
The ChaMP-332 is configured for production use with 300 mm and 200 mm silicon wafers, including notched and flat-edge variants compliant with SEMI MW109 and MW110 specifications.
Is optical endpoint detection included as standard equipment?
Yes—the integrated broadband optical endpoint system is factory-installed and calibrated, supporting real-time layer-thickness tracking for up to three stacked films simultaneously.
Can the ChaMP-332 be integrated into an automated factory material handling system?
The system includes SECS/GEM (SEMI E30/E37) communication interfaces and supports FOUP/SMIF loadport integration per SEMI E47.1 and E87 standards.
What level of process documentation and validation support is provided?
Accretech supplies IQ/OQ documentation packages, traceable calibration certificates for all critical sensors, and a comprehensive DQ protocol aligned with ISO 9001 and IATF 16949 quality management systems.
Does the ChaMP-332 comply with cleanroom environmental requirements?
The tool is rated for ISO 14644-1 Class 5 operation, with fully sealed fluid paths, HEPA-filtered exhaust recirculation, and non-shedding internal materials certified per SEMI F21.