TSD POLI-500 Chemical Mechanical Polishing System

Overview

The TSD POLI-500 Chemical Mechanical Polishing (CMP) System is an engineered platform for precision surface planarization in semiconductor front-end and advanced packaging processes. It operates on the fundamental principle of synergistic material removal—combining controlled chemical reactivity from slurry chemistry with deterministic mechanical abrasion induced by relative motion between the wafer, polishing pad, and conditioning elements. This dual-mechanism enables nanometer-level control over removal rate, uniformity, and surface topography across dielectric films (e.g., SiO₂), metal layers (e.g., Cu, Co, Ru), and emerging barrier/seed stacks used in logic, memory, and 3D heterogeneous integration applications. Designed for R&D, pilot-line validation, and low-volume production environments, the POLI-500 supports process development under GLP-aligned operational discipline and provides traceable parameter logging essential for technology transfer and qualification.

Key Features

• Compliant pneumatic bladder loading system ensures uniform downforce distribution across the entire wafer backside, minimizing edge effects and enhancing within-wafer non-uniformity (WIWNU) performance.
• Dual independent rotational axes—programmable platen (30–200 rpm) and carrier head (30–200 rpm)—enable precise tuning of relative velocity profiles to optimize removal rate and defectivity for diverse film stacks.
• Oscillating arm-type conditioner with selectable reciprocating motion delivers repeatable pad topography restoration while reducing groove depth variation and extending pad life.
• Three-channel peristaltic slurry delivery system allows independent flow control for oxidizer, abrasive, and pH-modifying components—critical for multi-step polishing sequences and slurry stability management.
• Modular architecture supports field-upgradable options including real-time friction force and thermal monitoring at the pad–wafer interface, as well as electrochemical endpoint detection (EPD) for Cu or W stop-layer identification.
• Semi-automated tray-based loading interface reduces manual handling exposure and improves alignment repeatability during wafer transfer—particularly advantageous for thin, warped, or temporary-bonded substrates.

Sample Compatibility & Compliance

The POLI-500 accommodates standard 200 mm (8-inch) wafers and is mechanically adaptable for smaller formats (100 mm, 150 mm) via configurable carrier head inserts. It supports both rigid silicon substrates and flexible carriers used in temporary bonding/debonding workflows common in fan-out wafer-level packaging (FOWLP) and through-silicon via (TSV) fabrication. The system’s mechanical design conforms to ISO 14644-1 Class 5 cleanroom compatibility requirements when operated within appropriate enclosures. All electrical subsystems meet CE safety directives (2014/35/EU), and firmware architecture supports audit-trail generation aligned with FDA 21 CFR Part 11 principles for electronic records and signatures—enabling use in GMP-compliant process development labs.

Software & Data Management

The POLI-500 is operated via a Windows-based HMI running proprietary control software with role-based access levels (Operator, Engineer, Administrator). All critical process parameters—including rotational speeds, downforce setpoints, slurry flow rates, and optional sensor outputs—are time-stamped and logged in binary+CSV format for post-run analysis. The software includes built-in recipe management with version control, parameter interlock safeguards (e.g., minimum platen speed before head rotation), and configurable alarm thresholds. Exported datasets are compatible with industry-standard statistical process control (SPC) tools and can be integrated into MES platforms via OPC UA or Modbus TCP protocols. Audit logs record user actions, parameter changes, and system events with immutable timestamps—supporting regulatory review and internal quality audits.

Applications

• Interlayer dielectric (ILD) planarization for BEOL integration in sub-28 nm node logic devices.
• Copper damascene polishing with endpoint-controlled removal to achieve <±2% thickness uniformity across 200 mm wafers.
• Barrier layer (e.g., TaN, Co) and ultra-low-k dielectric polishing for advanced interconnect schemes.
• Post-etch residue removal and surface smoothing prior to ALD nucleation in high-aspect-ratio structures.
• Wafer-level grinding/polish hybrid processes for TSV reveal and redistribution layer (RDL) formation in 2.5D/3D IC stacking.
• Process window characterization for novel slurry chemistries, pad materials, and conditioning strategies under controlled DOE frameworks.

FAQ

What wafer sizes does the POLI-500 support?
The system is configured for 200 mm (8-inch) wafers as standard; mechanical adaptation kits for 100 mm and 150 mm substrates are available upon request.
Is the EPD module compatible with non-copper metallization systems?
Yes—the electrochemical endpoint detection option supports configurable electrode configurations and potentiostatic protocols suitable for tungsten, cobalt, and ruthenium-based films.
Can the POLI-500 operate in a nitrogen-purged environment?
The base configuration is rated for ambient air operation; custom inert-gas purge integration (N₂ or Ar) is available as an engineering option for oxygen-sensitive slurries or reactive metal polishing.
Does the system include remote diagnostics capability?
Standard Ethernet connectivity enables secure remote monitoring and limited troubleshooting via TLS-encrypted VNC session; full remote control requires additional cybersecurity assessment per site IT policy.
What maintenance intervals are recommended for the peristaltic pump tubing?
Tubing replacement is advised every 200 operational hours or after 100 polishing runs—whichever occurs first—to ensure volumetric accuracy and prevent cross-contamination between slurry channels.