Thermo Scientific™ ELITE™ Integrated Lock-in Thermography System

Overview

The Thermo Scientific™ ELITE™ Integrated Lock-in Thermography System is a purpose-built, fully automated non-destructive failure analysis platform engineered for high-sensitivity dynamic thermal imaging of integrated circuits (ICs), advanced packages, and printed circuit assemblies. Leveraging lock-in thermography (LIT)—a phase-resolved infrared imaging technique that applies periodic electrical stimulation while synchronously detecting minute temperature modulations—the ELITE system achieves sub-micron spatial resolution in lateral (x–y) dimensions and ±20 µm depth localization accuracy. Unlike conventional steady-state thermal imaging or passive IR inspection, LIT suppresses background thermal noise through frequency-domain filtering, enabling detection of resistive anomalies, leakage paths, shorted interconnects, latch-up events, ESD-damaged junctions, and subtle oxide defects—even beneath multiple metal layers or embedded die stacks. As the industry’s first turnkey LIT solution supporting both 2D planar and 3D heterogeneous integration architectures (e.g., 2.5D/3D ICs, fan-out wafer-level packaging, silicon interposers), the ELITE system eliminates the need for decapsulation, deprocessing, or physical probing during early-stage root-cause analysis.

Key Features

• Proprietary high-frame-rate InSb focal plane array (FPA) cooled to 77 K, delivering thermal sensitivity < 10 mK at 1 Hz modulation frequency
• Custom-designed optical path with motorized zoom, autofocus, and optional Solid Immersion Lens (SIL) for diffraction-limited resolution down to 0.8 µm at 3.4 µm IR wavelength
• Integrated S-LSM (Scanning Laser Stimulation Module) for synchronized electro-optical stimulation and multi-modal defect correlation
• Real-time phase and amplitude image reconstruction with pixel-level lock-in demodulation (0.1–10 kHz range)
• Automated stage with 3-axis precision motion control (±0.1 µm repeatability) and tilt compensation for warped substrates
• Hardware-accelerated signal processing engine enabling full-frame LIT acquisition at up to 60 fps with on-the-fly Fourier transform

Sample Compatibility & Compliance

The ELITE system accommodates a broad spectrum of electronic test specimens—from bare die and flip-chip assemblies to multilayer PCBs, PoP (Package-on-Package), and chiplet-based systems—without mechanical modification or electrical interface alteration. It supports standard JEDEC trays, custom carriers, and vacuum chucks for thermal stabilization. All hardware and software components comply with ISO/IEC 17025 requirements for calibration traceability, and the system architecture adheres to FDA 21 CFR Part 11 principles for audit-ready electronic records, including user authentication, electronic signatures, and immutable activity logs. Data export formats conform to ASTM E2582 (Standard Guide for Infrared Thermography) and IPC-J-STD-033 for moisture-sensitive device handling documentation.

Software & Data Management

ELITE Control Suite v5.x provides an intuitive, workflow-driven interface with preconfigured test templates for common failure modes (e.g., “Power Short Mapping”, “ESD Junction Leakage Scan”, “Latch-up Triggering Protocol”). The software integrates native support for GLP/GMP-compliant reporting, automatic metadata tagging (stimulus parameters, ambient conditions, operator ID), and hierarchical data archiving compliant with IEEE 1622.2 (Standard for Failure Analysis Data Exchange). Raw thermal time-series datasets are stored in HDF5 format with embedded calibration coefficients; processed results—including phase maps, amplitude overlays, depth-sliced cross-sections, and correlated X-ray/SAM coordinate markers—are exportable as PDF, CSV, or TIFF with embedded EXIF-style metadata. Remote collaboration features include secure WebSocket-based session sharing and DICOM-compatible image streaming for cross-site FA lab coordination.

Applications

• Root-cause localization of resistive opens and current leakage paths in FinFET and GAA transistor structures
• Non-invasive identification of microvoids and intermetallic degradation in Cu–Sn solder joints under BGA packages
• Dynamic thermal profiling of power delivery networks (PDNs) during voltage droop events
• Correlative failure analysis with SAM and µCT: ELITE-provided (x,y,z) coordinates reduce X-ray scan volume by >90% and SAM raster time by up to 75%
• Qualification testing of wafer-level reliability (WLR) samples under accelerated aging conditions
• Verification of repair efficacy post-laser trimming or focused ion beam (FIB) edit without re-introducing process-induced artifacts

FAQ

What types of electrical stimuli are supported?
The system accepts DC bias, square-wave, sine-wave, and arbitrary waveform inputs via its integrated 4-quadrant source-measure unit (SMU), configurable from 0.1 V to 30 V and ±1 A, with programmable duty cycle and rise/fall times.
Can ELITE detect defects in stacked-die configurations?
Yes—through depth-resolved phase contrast imaging and multi-frequency LIT, the system resolves thermal signatures from individual die layers in 3D IC stacks up to 10 die thick, provided thermal coupling between layers is not fully conductive.
Is calibration required before each use?
No—factory-calibrated radiometric response is retained across power cycles; however, daily verification using NIST-traceable blackbody reference sources is recommended per ISO/IEC 17025 QA protocols.
How does ELITE integrate with existing FA lab workflows?
It exports standardized coordinate files (CSV/JSON) compatible with SEM/FIB navigation systems, SAM positioning controllers, and X-ray CT reconstruction pipelines—enabling seamless handoff without manual coordinate transformation.
Does the system support automated pass/fail classification?
Yes—via optional AI-assisted analytics module trained on >12,000 labeled defect images, supporting supervised classification of six primary failure categories with >94% precision in production environments.