EVG320 Automated Single-Wafer Wet Cleaning System

Overview

The EVG320 Automated Single-Wafer Wet Cleaning System is a high-precision, platform-based wet process tool engineered for front-end semiconductor manufacturing environments requiring sub-10 nm particle removal control and process reproducibility in advanced wafer-level packaging (WLP), hybrid bonding, and compound die-to-wafer (Co-D2W) integration. Operating on a sequential single-wafer transport architecture, the system implements controlled fluid dynamics, localized megasonic energy coupling (1 MHz transducer array), and programmable chemical delivery to achieve surface cleanliness compliant with JEDEC JESD22-B102 and SEMI F26 standards. Its modular station design supports multi-step cleaning sequences—including pre-rinse, chemical dispense (e.g., SC1, SC2, DHF), megasonic agitation, brush scrubbing (optional), and final DI water spin-rinse-dry—each executed under closed-loop environmental monitoring (temperature, flow rate, pressure, and dispense volume). The system is purpose-built for applications where surface integrity, oxide uniformity, and interfacial contamination control directly impact bond yield and void formation in 3D IC stacking and heterogeneous integration flows.

Key Features

• Full automation via dual-arm robotic handler with integrated pre-alignment stage for FOUP-to-FOUP or cassette-to-cassette transfer, supporting SECS/GEM communication protocols
• Four independently configurable cleaning stations enabling parallel process optimization for front-side, back-side, and bevel-specific treatments
• Megasonic cleaning module with 1 MHz transducers delivering uniform acoustic energy distribution across 4–12 inch wafers; optional zone-sensing feedback for real-time cavitation monitoring
• Brush cleaning station with adjustable rotational speed, normal force, and bristle material selection (e.g., polyvinyl alcohol or nylon) for controlled mechanical particle removal
• Chemical delivery subsystem supporting precise metering of diluted acids, bases, and surfactants with traceability down to ±0.5 mL per dispense cycle
• Hermetically sealed process chambers with laminar N₂ purge to suppress airborne molecular contamination (AMC) during critical rinse/dry phases
• Integrated remote diagnostics suite compliant with IEEE 1621, enabling predictive maintenance alerts and secure technician access via TLS-encrypted VNC tunnel

Sample Compatibility & Compliance

The EVG320 accommodates bare silicon, SOI, glass, compound semiconductor (GaAs, SiC, InP), and thin-film metalized substrates ranging from 100 mm (4 inch) to 300 mm (12 inch) in diameter. All wet chemistry contact surfaces are constructed from PFA-lined 316L stainless steel and quartz to ensure compatibility with aggressive chemistries including hydrofluoric acid blends and ozone-enhanced water. The system meets ISO 14644-1 Class 5 cleanroom requirements when installed with appropriate facility interfaces and complies with CE Machinery Directive 2006/42/EC, PED 2014/68/EU, and RoHS 2011/65/EU. For regulated environments, optional 21 CFR Part 11-compliant electronic signature and audit trail modules support GMP/GLP-aligned validation documentation.

Software & Data Management

Controlled by EVG’s proprietary CleanMaster™ software platform, the EVG320 provides full recipe-based operation with hierarchical user access levels (Operator, Engineer, Administrator). Each process step logs timestamped metadata—including chamber temperature, chemical lot ID, dispense volume, rotation speed, and megasonic power output—to an embedded SQL database. Data export supports CSV, XML, and SECS-II HSMS formats for integration into factory MES systems. Audit trail functionality records all parameter modifications, login/logout events, and alarm acknowledgments with immutable hashing for FDA inspection readiness.

Applications

• Pre-bond surface conditioning for fusion and hybrid bonding processes in 3D NAND and HBM stacks
• Post-lithography residue removal prior to Cu reflow or microbump formation
• Particle removal after thin-film deposition (e.g., ALD TiN, PVD TaN) without compromising interface stoichiometry
• Bevel and edge exclusion zone cleaning to prevent delamination in wafer-level chip-scale packaging (WLCSP)
• Recovery cleaning of reclaimed wafers in R&D and pilot-line settings

FAQ

What wafer handling standards does the EVG320 support?
The system natively supports SEMI E47.1-compliant FOUPs (300 mm) and standard 25-wafer cassettes (100–200 mm), with optional adapters for SMIF pods.
Is backside cleaning available as a standard configuration?
Backside cleaning is offered as a configurable option with dedicated nozzles and isolated fluid manifolds to prevent cross-contamination between front and back surfaces.
Can the EVG320 be integrated into a cluster tool environment?
Yes—the system features standard vacuum load-lock interface options and supports SECS/GEM communication for seamless integration with track systems and lithography platforms.
What level of particle removal efficiency is validated for this tool?
EVG reports ≥99.9% removal of ≥50 nm latex sphere particles (LSP) on silicon wafers under optimized megasonic + brush + SC1 conditions, per SEMI MF-T5-0504 test methodology.
Does the system include qualification documentation for ISO 9001-certified fabs?
Factory acceptance testing (FAT) packages include IQ/OQ documentation templates aligned with ISO/IEC 17025 and can be extended to full PQ execution upon request.