Neutron Scattering Data Acquisition Electronics System

Overview

The Neutron Scattering Data Acquisition Electronics System is a high-performance, FPGA-based digital readout platform engineered specifically for time-of-flight (TOF) neutron scattering instruments at spallation sources and reactor-based facilities. It implements event-driven acquisition architecture—capturing individual neutron detection events with precise temporal and spatial metadata—enabling full-spectrum reconstruction, pulse-shape discrimination, and multi-detector coincidence analysis. Unlike legacy histogramming systems, this electronics suite preserves raw event-level data (time, channel ID, pulse height, detector group), supporting post-acquisition rebinning, background subtraction, and advanced correlation analysis without hardware reconfiguration. Its timing engine is synchronized to the neutron source’s master clock (e.g., accelerator RF or chopper phase), ensuring sub-100 ns timestamp accuracy referenced to the TOF zero point (t₀)—a critical requirement for high-resolution diffraction, small-angle scattering (SANS), and inelastic spectroscopy.

Key Features

• FPGA-based real-time signal processing: Xilinx Kintex Ultrascale+ FPGA implements configurable digital pulse shaping, baseline restoration, leading-edge discrimination, and dead-time compensation—optimized for ³He, ¹⁰B, Gd-based, and scintillator-based detectors.
• Event-driven acquisition firmware: Records each validated detection event as a structured 64-bit packet containing 48-bit absolute timestamp (referenced to t₀), 12-bit detector address, 4-bit energy bin (optional), and validity flags—enabling lossless streaming at sustained rates >5 MHz per input channel.
• TOF-optimized timing subsystem: Integrated low-jitter PLL and temperature-compensated oscillator deliver stable 100 ns time bin resolution across 48-bit counter range (0–325 days), supporting both absolute timestamping and relative Δt measurements between correlated events.
• Modular I/O architecture: Supports up to 256 parallel detector channels via LVDS or NIM inputs; optional optical fiber uplinks for remote detector arrays; PCIe Gen3 x8 host interface for direct memory-mapped data transfer to Linux-based DAQ servers.
• Ruggedized industrial design: Conforms to EN 61000-6-2/6-4 EMC standards; operates continuously at 0–45 °C ambient; designed for rack-mounted deployment in neutron instrument hutches with radiation-hardened PCB layout (≤10 krad(Si) TID tolerance).

Sample Compatibility & Compliance

This system does not interact directly with physical samples but serves as the foundational electronic layer for neutron detection instrumentation used across materials science, condensed matter physics, and soft matter research. It is fully compatible with standard neutron detector technologies—including position-sensitive ³He tubes, microchannel plate (MCP) detectors, and scintillator arrays coupled to SiPMs—and integrates seamlessly with major neutron facility control frameworks (EPICS, TANGO, Sardana). The firmware and data format adhere to the NeXus/HDF5 standard (NXevent_data class), ensuring interoperability with Mantid, DAWN, and other ILL/ESS/ANL-standard analysis tools. All timestamped event data meets audit-trail requirements for GLP-compliant experiments and supports 21 CFR Part 11–aligned metadata logging when deployed with certified DAQ software stacks.

Software & Data Management

The system ships with open-source firmware (VHDL/Verilog) and a Linux-compatible device driver stack (kernel module + userspace library), enabling integration into custom or facility-wide DAQ environments. The reference acquisition software—NeuDAQ—provides real-time monitoring, live histogramming, event filtering, and HDF5 streaming with configurable compression (Blosc/LZ4). All timestamps are stored in ISO 8601-compliant UTC format with nanosecond precision, and metadata includes provenance fields (source period, chopper phase, sample environment status, beamline configuration). Data provenance is enforced via cryptographic hashing of raw event buffers and write-once filesystem support for long-term archival integrity. Optional validation packages include NIST-traceable timing calibration reports and IEC 62443-3-3 cybersecurity hardening modules for network-connected deployments.

Applications

• Time-of-flight neutron diffraction for crystallographic phase mapping and magnetic structure determination.
• Small-angle neutron scattering (SANS) studies of polymer self-assembly, protein folding, and nanoparticle dispersion.
• Inelastic neutron scattering (INS) experiments measuring phonon and magnon dispersions in quantum materials.
• Reflectometry investigations of thin-film interfaces and buried layer dynamics under in situ conditions.
• Development and commissioning of next-generation neutron spectrometers requiring high-throughput, low-latency event recording and flexible offline analysis pipelines.

FAQ

What neutron source types is this system compatible with?
It supports pulsed sources (e.g., ESS, SNS, J-PARC) and continuous sources with chopper-based TOF modulation, provided the facility provides a TTL or LVDS t₀ synchronization signal.
Can the timestamp resolution be improved beyond 100 ns?
The base hardware resolution is fixed at 100 ns; however, interpolation techniques using analog pulse arrival time estimation (via TDC+ADC hybrid mode) can achieve effective sub-ns resolution in select configurations—subject to detector rise-time limitations.
Is the FPGA firmware customizable for proprietary detector interfaces?
Yes—full VHDL source code and synthesis toolchain documentation are provided under a facility-use license, enabling adaptation to non-standard detector signal protocols or custom trigger logic.
Does the system support real-time data reduction during acquisition?
Basic histogramming and region-of-interest (ROI) counting are implemented in FPGA; full spectral reduction (e.g., vanadium normalization, Q-transformation) occurs offline in Mantid or custom Python workflows.
How is radiation damage mitigated in long-term operation?
Critical components are selected from radiation-tolerant vendor lists; PCB layout follows single-event upset (SEU) mitigation practices; periodic scrubbing of FPGA configuration memory is supported via watchdog-triggered reconfiguration.