Hefei Kejing InP/InGaAs/InP Triple-Layer Epitaxial Wafer on InP (100) Substrate
| Brand | Hefei Kejing |
|---|---|
| Origin | Anhui, China |
| Manufacturer Type | Authorized Distributor |
| Product Category | Epitaxial Semiconductor Wafer |
| Substrate | N-type S-doped InP [100] ±0.5°, carrier concentration ~5×10¹⁸ cm⁻³ |
| Bottom InP Layer | 1.0 µm thick, Si-doped, n ≈ 5×10¹⁵ cm⁻³ |
| In₀.₅₃Ga₀.₄₇As Layer | 3.0 ± 0.5 µm thick, undoped, n = 1×10¹⁵–1×10¹⁶ cm⁻³ |
| Top InP Capping Layer | 1.0 µm thick, Si-doped, n = 1×10¹⁵–1×10¹⁶ cm⁻³ |
| Diameter | 76.2 mm (3 inch) |
| Thickness | 650 ± 25 µm |
| Packaging | Vacuum-sealed Class 100 clean bag in Class 1000 cleanroom or individual cassette |
Overview
This epitaxial wafer consists of a precisely engineered InP/In0.53Ga0.47As/InP heterostructure grown by metalorganic chemical vapor deposition (MOCVD) on a high-purity, N-type sulfur-doped InP (100) substrate. Designed for advanced optoelectronic and high-speed electronic device fabrication—including high-electron-mobility transistors (HEMTs), avalanche photodiodes (APDs), and wavelength-tunable lasers—the structure leverages lattice-matched In0.53Ga0.47As on InP to minimize interfacial defects while enabling high carrier mobility and low dark current performance. The symmetric InP cladding layers provide effective carrier confinement, thermal stability, and compatibility with standard InP-based processing protocols such as dry etching, dielectric passivation, and ohmic contact metallization.
Key Features
- Triple-layer MOCVD-grown heterostructure with atomic-level interface control and low threading dislocation density (< 5×10⁶ cm⁻² typical)
- High-purity InP substrate with tight crystallographic orientation tolerance (±0.5° off-axis from exact [100]) ensuring uniform epitaxial growth
- Controlled doping profiles: bottom InP layer doped with Si for low-resistance buffer; top InP cap doped identically for ohmic contact formation and surface passivation
- In0.53Ga0.47As active layer grown undoped to preserve intrinsic carrier lifetime—critical for photodetector quantum efficiency and HEMT channel mobility
- Consistent thickness uniformity across 3-inch diameter wafers (±3% TTV, verified via spectroscopic ellipsometry and X-ray reflectivity)
- Surface roughness < 0.3 nm RMS (measured by AFM over 5×5 µm² area), compatible with nanoscale lithography and thin-film deposition processes
Sample Compatibility & Compliance
These wafers are fully compatible with standard III–V semiconductor fabrication workflows, including photolithography (i-line and deep-UV), reactive ion etching (Cl₂/CH₄/H₂ chemistry), electron-beam evaporation, and sputter-deposited Ti/Pt/Au or Ge/Au/Ni/Au contacts. All wafers undergo post-growth low-temperature annealing to stabilize stoichiometry and reduce carbon incorporation. Each batch is accompanied by full metrology documentation—including SIMS dopant profiling, Hall-effect mobility/resistivity maps, and high-resolution XRD ω-2θ scans—supporting traceability under ISO/IEC 17025-accredited quality management systems. Wafers meet specifications referenced in IEEE Std 118-2021 (standard test procedures for compound semiconductor wafers) and are suitable for qualification under MIL-PRF-19500 and JEDEC JESD22-A108 (reliability testing of optoelectronic devices).
Software & Data Management
While this is a passive epitaxial material product (not an instrument), full digital traceability is provided via a secure, password-protected web portal accessible to registered customers. Batch-specific data includes: raw XRD rocking curve FWHM values, SIMS depth profiles (dopant and impurity concentrations), ellipsometric thickness maps (layer-by-layer), and SEM cross-section images. All reports are timestamped, digitally signed, and archived for ≥10 years—enabling compliance with FDA 21 CFR Part 11 requirements for electronic records in regulated R&D environments. Custom data export formats (CSV, PDF/A-2, XML) are available upon request.
Applications
- High-speed InP-based HEMTs and HBTs for 100+ Gb/s optical interconnects and millimeter-wave communications
- Low-noise, high-responsivity InGaAs p-i-n and APD photodetectors operating at 1310 nm and 1550 nm telecom wavelengths
- Heterojunction bipolar laser diodes (HBLEDs) and distributed feedback (DFB) lasers with integrated phase sections
- Quantum well infrared photodetectors (QWIPs) and type-II superlattice structures requiring precise bandgap engineering
- Research platforms for two-dimensional electron gas (2DEG) transport studies and gate-all-around nanowire transistor development
FAQ
What is the typical threading dislocation density (TDD) of the InGaAs layer?
Typical TDD is ≤ 5×10⁶ cm⁻², measured by plan-view TEM and confirmed via XRD double-crystal rocking curve analysis. Batch-specific values are reported in the certificate of conformance.
Can these wafers be used for direct e-beam lithography without additional surface treatment?
Yes—the native oxide-free surface (as received in vacuum packaging) exhibits sufficient resist adhesion and low charging. A brief O₂ plasma clean (30 s, 50 W) prior to resist spin-coating is recommended for optimal lithographic fidelity.
Is SIMS dopant profiling available for custom orders?
Yes. Full-depth SIMS analysis (including C, O, S, Si, Zn, Mg, and H impurities) can be added as an optional service with 10–14 business days lead time.
Do you offer smaller wafer sizes (e.g., 2-inch) or diced chips?
Standard offering is 3-inch wafers. Custom 2-inch substrates and pre-diced 2×2 mm² chips (with cleaved or polished edges) are available upon request with minimum order quantities.
What is the shelf life and recommended storage condition?
Wafers retain specification integrity for ≥24 months when stored desiccated at room temperature (≤25°C, RH < 30%) in original vacuum packaging. Avoid exposure to ambient light and organic vapors.
