RTI MT Century Automated Curve Tracer for Semiconductor IC Testing

Overview

The RTI MT Century Automated Curve Tracer is a precision-engineered DC parametric test system designed specifically for semiconductor device characterization and failure analysis in IC manufacturing, packaging, and independent test laboratories. Operating on the fundamental principle of voltage-swept current measurement (I-V curve tracing), the system applies controlled DC stimuli across device pins while simultaneously measuring resulting currents and voltages—enabling rapid identification of electrical defects including opens, shorts, leakage paths, abnormal supply current draw (I_DD, I_DDQ), and latch-up susceptibility. Unlike generic source-measure units (SMUs), the MT Century integrates purpose-built hardware architecture—including high-accuracy 16-bit DACs, low-noise 24-bit ADCs, and programmable relay matrices—with semiconductor-specific test sequencing logic to deliver repeatable, traceable, and standards-aligned parametric data acquisition. Its modular design supports both unpowered (passive) and powered (active) curve tracing modes, making it suitable for wafer-level probing, packaged device screening, and post-failure root-cause analysis.

Key Features

• Scalable channel architecture supporting up to 96 independently configurable test channels, with pin-mapped addressing for precise DUT interface control.
• Dual-mode operation: Unpowered curve tracing (0 V bias) for continuity and insulation resistance verification; Powered curve tracing (±15 V, ±1 A compliance) for functional parametric assessment under bias.
• Integrated 6-bus power supply measurement system enabling simultaneous characterization of multiple V_DD/V_SS domains—supporting 2-VDD, 3-VDD, and multi-rail IC configurations.
• Latch-up testing capability compliant with JEDEC Standard JESD78 (IC Latch-Up Test Methodology), including programmable stress duration, ramp rate, and recovery monitoring.
• Kelvin 4-wire resistance measurement mode with automated switch matrix control for low-resistance (100 MΩ) applications.
• Functional stimulus sequencing engine: Accepts user-defined input pin state files (e.g., CSV or ASCII patterns) and synchronizes output state capture for gross functional validation without requiring external ATE infrastructure.

Sample Compatibility & Compliance

The MT Century accommodates a broad range of semiconductor packages—from bare die and wafer-level devices (via probe station integration) to QFP, BGA, SOIC, and CSP formats—using RTI’s standardized mechanical interface (compatible with 950-series fixtures and third-party handlers). All measurement subsystems comply with ISO/IEC 17025 calibration traceability requirements when operated within specified environmental conditions (23 ± 2 °C, <60% RH). The system supports audit-ready data logging aligned with GLP and GMP frameworks, including full timestamping, operator ID tagging, and instrument configuration snapshots per test execution. While not FDA-certified as standalone medical equipment, its data integrity features—including write-once file export and optional 21 CFR Part 11-compliant electronic signature modules—meet foundational requirements for regulated semiconductor qualification workflows.

Software & Data Management

Controlled via RTI’s MultiTrace Studio software suite (Windows 10/11 compatible), the MT Century provides intuitive graphical test setup, real-time waveform visualization, and automated report generation in PDF, CSV, and XML formats. The software architecture includes built-in scriptability (TCL/Lua), API access for factory MES integration (SECS/GEM, STDF export), and configurable pass/fail limits with statistical process control (SPC) charting. All raw I-V datasets are stored with metadata including test date/time, DUT lot ID, operator credentials, and hardware calibration status—ensuring full traceability from test execution to final disposition. Optional database connectors (ODBC, SQL Server) enable centralized result aggregation across multi-system test floors.

Applications

• Pre-bond and post-packaging continuity verification (open/short detection) using unpowered curve tracing.
• Supply current profiling (I_DD, I_DDQ) across functional states for low-power design validation.
• Transistor-level characterization (FET transfer curves, diode IV sweeps) for process monitor vehicle analysis.
• Latch-up immunity screening of mixed-signal and RF SoCs per JEDEC JESD78 Class I–III stress levels.
• Failure analysis support via correlation with optical microscopy or emission imaging—leveraging pin-level fault localization from curve anomalies.
• Qualification testing of automotive-grade ICs (AEC-Q100 stress categories) where parametric stability under thermal cycling is critical.

FAQ

What is the maximum pin count supported by the MT Century system?

The MT Century is configured for up to 96 test channels; however, through multiplexed scanning and sequential pin addressing, it can characterize devices with >1,000 pins via programmable test plan sequencing.

Does the system support automated calibration verification?

Yes—integrated self-test routines verify source accuracy, meter linearity, and relay contact resistance at startup and on scheduled intervals, with results logged to the audit trail.

Can the MT Century interface with third-party probe stations or handler systems?

Absolutely—the system features standard GPIB, USB-TMC, and Ethernet (VISA) interfaces, plus native support for common handler protocols (e.g., Advantest T2000, Teradyne UltraFlex) via optional driver packs.

Is latch-up testing performed in accordance with industry standards?

All latch-up routines implement JEDEC JESD78-defined stress profiles—including Class I (100 mA), Class II (200 mA), and Class III (500 mA)—with configurable ramp rates, hold times, and automatic current limiting.

How does the MT Century ensure measurement repeatability across shifts and operators?

Through hardware-level calibration traceability, software-enforced test plan version control, and operator-authenticated session initiation—each test record contains immutable configuration fingerprints and environmental metadata.